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Chip Ecosystem Apprenticeships Help Close The Talent Gap

Competency-based apprenticeship programs are gaining wider acceptance across the chip industry as companies and governments look for new ways to address talent shortages, and as workers look for new...

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Why Chiplets Are So Critical In Automotive

Chiplets are gaining renewed attention in the automotive market, where increasing electrification and intense competition are forcing companies to accelerate their design and production schedules....

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Backside Power Delivery Gears Up For 2nm Devices

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower...

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Chip Industry Week In Review

By Adam Kovac, Karen Heyman, and Liz Allan. India approved the construction of two fabs and a packaging house, for a total investment of about $15.2 billion, according to multiple sources. One fab will...

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Digital Twins Target IC Tool And Fab Efficiency

Digital twins have emerged as the hot “new” semiconductor manufacturing technology, enabling fabs to create a virtual representation of a physical system on which to experiment and optimize what’s...

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Chip Industry Week In Review

Applied Materials may scale back or cancel its $4 billion new Silicon Valley R&D facility in light of the U.S. government’s recent announcement to reduce funding for construction, modernization, or...

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Memristor Crossbar Architecture for Encryption, Decryption and More

A new technical paper titled “Tunable stochastic memristors for energy-efficient encryption and computing” was published by researchers at Seoul National University, Sandia National Laboratories, Texas...

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What Works Best For Chiplets

The semiconductor industry is preparing for the migration from proprietary chiplet-based systems to a more open chiplet ecosystem, in which chiplets fabricated by different companies of various...

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Chip Industry Week In Review

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how...

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Chip Industry Technical Paper Roundup: April 30

These new technical papers were recently added to Semiconductor Engineering’s library. Technical Paper Research Organizations Quantum interference enhances the performance of single-molecule...

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Chip Industry Week In Review

JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior...

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Digital Twins Find Their Footing In IC Manufacturing

Momentum is building for digital twins in semiconductor manufacturing, tying together the various processes and steps to improve efficiency and quality, and to enable more flexibility in the fab and...

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Chip Industry Week In Review

The U.S. Department of Commerce issued a notice of intent  to fund new R&D activities to establish and accelerate domestic advanced packaging capacity. CHIPS for America expects to award up to $1.6...

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New Interconnect Metals Need New Dielectrics

Just as circuit metallization must evolve to manage resistance as features shrink, so must the dielectric half of the interconnect stack. For quite some time, manufacturers have needed a dielectric...

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Chip Industry Week in Review

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and...

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Chip Industry Week in Review

The Biden-Harris Administration announced preliminary terms with HP for $50 million in direct funding under the CHIPs and Science Act to support the expansion and modernization of HP’s existing...

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New Materials Are in High Demand

Materials suppliers are responding to the intense pressures to improve power, performance, scaling, and cost issues, which follows a long timeline from synthesis to development and high volume...

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Optimizing Wafer Edge Processes For Chip Stacking

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower...

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Americas Chip Funding Energizes Industry

This is the second in a series of articles tracking government chip investments. See part one here. Part 3 and 4 of the series will cover Europe and Asia. Since the first announcement of a non-binding...

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Hybrid Bonding Makes Strides Toward Manufacturability

Hybrid bonding is gaining traction in advanced packaging because it offers the shortest vertical connection between dies of similar or different functionalities, as well as better thermal, electrical...

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