Better nanowire MOSFETs
At the recent IEEE International Electron Devices Meeting (IEDM), Imec and Applied Materials presented a paper on a new and improved way to fabricate vertically stacked gate-all-around MOSFETs.
More specifically, Imec and Applied reported on process improvements for a silicon nanowire MOSFET, which is integrated in a CMOS dual work function metal replacement metal gate (RMG) flow.
The nanowire MOSFET and a related device, the nanosheet MOSFET, are aimed to replace today’s finFET transistors at some point in the future. In both cases, a finFET is placed on its side and is then divided into separate horizontal pieces, which make up the channels. A gate wraps around the channel. Compared to nanowires, the nanosheet FET has a wider channel.
Meanwhile, compared to previous work, Imec and Applied have made process improvements for the shallow trench isolation (STI), reduced vertical nanowires spacing, integration of a thinner nMetal process with low Vth capability, and DC/AC performance improvement.
In this work, the nanowire FETs are made on standard 300mm bulk CMOS wafers. In the flow, the first step is to make a super-lattice structure on a substrate using an epitaxial reactor. The super-lattice consists of alternating layers of silicon-germanium (SiGe) and silicon.
Then, a fin is patterned. The STI fill module is then performed, followed by dummy gate patterning, according to Imec and Applied Materials. “In-situ doped S/D (source/drain) are made up of highly-doped Si:P for NMOS and SiGe:B+Si:B liner (used as a protection barrier for S/D during NW release) for PMOS, with the flow available in both NMOS or PMOS epi S/D first integration schemes,” said Romain Ritzenthaler, device and characterization engineer at Imec and lead author of the paper.
Then, the SiGe layers are selectively removed in the super-lattice structure, followed by a dual work function RMG scheme. “By reducing the STI thermal budget and introducing a SiN STI liner, a reduced NW size loss and better shape controllability are demonstrated,” Ritzenthaler said. “Thanks to reduced STI oxidation, larger wires (featuring a width of 15nm and height of 11nm) with improved width/height aspect ratio can also be demonstrated.”
A device with reduced vertical nanowire spacing (12nm to 8nm) has been fabricated. With an improvement of ION/IOFF performance, a ring oscillator gate delay improvement from 24ps down to 10ps at matched VDD has also been demonstrated.
SOI nanosheets
In a separate paper at IEDM, CEA-LETI, STMicroelectronics and SERMA Technologies presented its results on a nanosheet FET based on silicon-on-insulator (SOI) wafers.
The transistors are processed on 300mm SOI substrates, with a replacement metal gate (RMG) process and self-aligned contacts. Variable sheets with widths up to 50nm have been demonstrated.
As with other FD-SOI devices, this technology also has back-biasing capabilities. “Back-biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels,” said Sylvain Barraud from CEA-LETI and lead author of the paper. “This allows to consider an additional lever to offer more power/performance flexibility in 3D stacked channels.
“Advanced electrical characterization of these devices enabled us to calibrate a new version of a physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels,” Barraud said.
What is iCVD?
Also at IEDM, KAIST, Lam Research and the Korea Aerospace University described a novel doping technique called an initiated CVD process or iCVD.
The process is tuned for an ultra-thin body (UTB) or SOI finFET. “To continue the success of the semiconductor industry even beyond the 10nm technology node, an ultra-thin body (UTB) in the form of a finFET and/or a SOI would be indispensable to minimize the undesirable short-channel effect,” said Jae Hwan Kim, a researcher at KAIST and one of the authors of the paper.
“However, this UTB approach faces more challenges with regard to process integration. Particularly, a conformal and high concentration doping technique within fin arrays has become a critical issue on next- generation devices. Conventional ion-implantation causes non-conformal doping and structural damage to the UTB, resulting in the degradation of the device performance,” Kim said.
Enter iCVD. This novel technique enables conformal, wafer-scale and controlled nanoscale doping of semiconductors at a high concentration. “To achieve a high doping concentration from a sub-10nm layer, an optimized integration process was developed in which copolymer p(BAO-co-V3D3) passivation for pBAO and double-step deposition for pTAP were used. This doping technique was successfully implemented with a SOI nFET. The proposed iCVD doping method showed the low enough sheet resistance for both the n-type and the p-type,” Kim said.
“The SOI nFET with iCVD doping at the source/drain regions exhibited better sub-threshold swing and on-current values than a SOI nFET with conventional ion implantation doping,” Kim said. “Compared to other diffusion doping methods, the iCVD process could achieve lower sheet resistance.”
