New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Parameters of performance: A deep dive into liquid-to-air CDU assessment | Binghamton University-SUNY and NVIDIA |
| Spiking Transformer Hardware Accelerators in 3D Integration | UC Santa Barbara, Georgia Tech and Burapha University |
| Sustainable Hardware Specialization | National University of Singapore and Ghent University |
| Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling | Belgium Research Center, Huawei Technologies and Global TCAD Solutions |
| Roadmap for Schottky Barrier Transistors | University of Surrey, NaMLab gGmbH, Forschungszentrum Jülic, Peter Grünberg Institute, et al. |
| GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package | University of Florida and University of Central Florida |
| Dual-Layer Thin-Film Transistor Analysis and Design | Oregon State University and Applied Materials |
| Implementation of Negative Differential Resistance-Based Circuits in Multigate Ge Transistors | TU Wien and JKU |
| MegaMmap: Blurring the Boundary Between Memory and Storage for Data-Intensive Workloads | Illinois Institute of Technology |
| Solving the Annealing of Mo Interconnects for Next-Gen Integrated Circuits | National University of Singapore, A*STAR, and imec |
The post Chip Industry Technical Paper Roundup: Nov. 25 appeared first on Semiconductor Engineering.
