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Chip Industry Week in Review
Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and...
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Chip Industry Week in Review
The Biden-Harris Administration announced preliminary terms with HP for $50 million in direct funding under the CHIPs and Science Act to support the expansion and modernization of HP’s existing...
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New Materials Are in High Demand
Materials suppliers are responding to the intense pressures to improve power, performance, scaling, and cost issues, which follows a long timeline from synthesis to development and high volume...
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Optimizing Wafer Edge Processes For Chip Stacking
Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower...
View ArticleAmericas Chip Funding Energizes Industry
This is the second in a series of articles tracking government chip investments. See part one here. Part 3 and 4 of the series will cover Europe and Asia. Since the first announcement of a non-binding...
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Hybrid Bonding Makes Strides Toward Manufacturability
Hybrid bonding is gaining traction in advanced packaging because it offers the shortest vertical connection between dies of similar or different functionalities, as well as better thermal, electrical...
View ArticleAnalysis And Design Of Dual-Layer TFTs (Oregon State Univ., Applied Materials)
A new technical paper titled “Dual-Layer Thin-Film Transistor Analysis and Design” was published by researchers at Oregon State University and Applied Materials. Abstract “A set of analytical equations...
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Chip Industry Week In Review
SK hynix started mass production of 1-terabit 321-high NAND, with availability scheduled for the first half of next year. Rapidus will receive an additional ¥200 billion yen ($1.28B) from the Japanese...
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Chip Industry Technical Paper Roundup: Nov. 25
New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Parameters of performance: A deep dive into liquid-to-air CDU assessment Binghamton...
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NAND Flash Targets 1,000 Layers
The chip industry is pushing to quadruple the stack height of 3D NAND flash from 200 layers to 800 layers or more over the next few years, using the additional capacity will help to feed the unending...
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